1. Technical Field
The present invention relates generally to a digital video system. In particular, the present invention relates to an apparatus and method for extracting vertical and horizontal synchronization signals from a digital composite synchronization signal.
2. Related Art
In certain video applications, it is often necessary to align an external (or master) video source with an internal second video source such that the two video sources operate at the same pixel clock frequency, and utilize common vertical and horizontal synchronization (sync) timings.
A digital video sync separator can be used to extract vertical (V-SYNC) and horizontal (H-Blank) sync signals from a digital composite sync signal (C-SYNC) of one video source (master) for use in controlling a second video source. Different applications and system configurations, however, may require different delay relationships (due, e.g., to varying latency in the secondary video path) between the composite video signal (C-SYNC) of the master video source and the generated horizontal (H-Blank) and vertical (V-SYNC) sync signals used to synchronize the second video source. To address the problem of a variable delay relationship between C-SYNC and H-Blank, a fixed delay is often inserted in the H-Blank and V-SYNC signals between the sync separator and the second video source. This fixed delay solution, however, does not provide the flexibility required to adjust to changing application requirements or alternate system configurations.
A need therefore exists to be able to control this delay relationship in a programmable fashion to allow for adjustment based on specific application requirements and system configurations.
A digital genlocking circuit (i.e., a circuit for the synchronization of one or more signals to another signal) can be used to adjust the pixel clock frequency of the system creating the second video stream, such that it is operating at the same frequency as the master composite video source. Known genlocking circuits often establish this fixed relationship by generating a control signal (e.g., a control voltage) based on the phase relationship (or delay) between the two events that are to be synchronized, and using the control voltage to feed a charge pump that directly controls a voltage controlled oscillator (VCXO). Variability in the responsiveness of such a genlocking device, however, may be desirable. For example, when the master video source is noisy, and the extracted composite sync signal exhibits some degree of jitter, a slower reacting adjustment to the VCXO control signal is desirable to dampen the resultant jitter in the second video signal. Similarly, when the master video signal is extremely stable, a quick reacting VCXO control signal will allow a very precise lock to the master frequency. To address the VCXO control voltage gain adjustment, previous solutions often involve changing the cutoff frequency of an RC filter on the input of the VCXO. Unfortunately, this has limited flexibility, requiring the changing of either the R or C value (or both) of the RC filter.
A need therefore exists for a degree of programmable variable gain in the genlocking circuit such that the responsiveness of the control to the VCXO may be selected based on the stability of the master video source or other criteria.
The present invention provides an apparatus and method for extracting V-SYNC and H-Blank signals from a digital composite sync signal (C-SYNC) (e.g., a master video source), which allows for an adjustable delay relationship between the C-SYNC from the master source and the generated H-Blank. The present invention also provides a system and method for varying the responsiveness or gain of the genlocking circuit used to synchronize the system pixel clock frequency of the second video source to that of the master video signal.
Generally, the present invention provides an apparatus comprising:
a first video source for providing a composite sync signal (C-SYNC);
a sync separator for extracting a horizontal sync signal (H-Blank) and a vertical sync signal (V-SYNC) from C-SYNC;
a system for measuring a delay between an edge of C-SYNC and H-Blank;
a comparator for comparing the measured delay with a programmable target delay value;
a pixel clock system for generating a pixel clock signal for a second video source, the second video source additionally receiving H-Blank and V-SYNC; and
a system for programmably controlling a duty cycle and effective gain of a digital signal provided to the pixel clock system, based on the comparison result provided by the comparator.
In addition, the present invention provides a method including the steps of:
providing a composite sync signal (C-SYNC) from a first video source;
extracting a horizontal sync signal (H-Blank) and a vertical sync signal (V-SYNC) from C-SYNC;
measuring a delay between an edge of C-SYNC and H-Blank;
comparing the measured delay with a programmable target delay value;
generating a pixel clock signal for a second video source, the second video source additionally receiving H-Blank and V-SYNC; and
programmably controlling a duty cycle and effective gain of a digital signal provided to the pixel clock system, based on the result of the comparison step.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention.